Fast Models Reference Manual - ARM Information Center

Processor Components
Message configuration
The parameters listed in Table 4-36 control how warning and error messages from the
architectural checkers are generated.
Table 4-36 Message severity levels
Parameter Description Default
messages.break_warning_level
The simulation stops in the debugger after emitting a
message at this level or higher.
5
messages.ignore_warning_level Messages below this level are ignored and not printed. 1
messages.suppress_repeated_messages
messages.output_file
The simulation does not emit more than one copy of a
message when it is generated from a given point in the
target program.
The path a of the file to which messages are written. If blank,
messages are sent to stderr.
true
a. The format of the string follows the normal file path conventions for the host platform. File paths without a leading root
are written into the current working directory, which might vary.
Except for fatal errors, the severity level of each message can be reconfigured in parameters
messages.severity_level_[*], allowing you to concentrate only on those warnings that are
appropriate to your task. See Table 4-37.
Level Name Description
0 Minor Warning Suspect, but plausibly correct
1 Warning A likely bug
Table 4-37 Message configuration parameters
2 Severe Warning Technically legal, but believed certain to be a bug
3 Error A definite architectural violation
4 Severe Error Target code unlikely to be able to recover
5 Fatal From which the simulation is unable to continue
4.12.4 Registers
The ARMAEMv7AMPCT model provides the registers specified by the technical reference
manual for the AEMv7 with the following exceptions:
• coprocessor 14 registers are not implemented
• integration and test registers are not implemented.
4.12.5 Caches
The ARMAEMv7AMPCT model implements L1 and L2 cache as architecturally defined.
4.12.6 Debug Features
The ARMAEMv7AMPCT model exports a CADI debug interface.
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