Fast Models Reference Manual - ARM Information Center

AEM ARMv7-A specifics
When stepping through programs in Model Debugger, a reordered load is evident when the
destination register of a load instruction is displayed as 0xAFAFAFAF (or 0xAFAF or 0xAF for
sub-word operations). The real value is loaded into the destination register when that value is
required for an operation that cannot be deferred any further, for example when it is used to
compute the address of a subsequent memory access.
If the value is never needed, for example when another value is written into the destination
register before it is ever read, then the deferred operation is killed instead. In such cases, it is
likely that the load operation is not visible from outside the core, and it also does not cause its
usual side-effects such as filling cache lines.
A.1.10
Other checks
The checks that are described in this section are always enabled. You can, however, suppress
any message from being printed by adjusting the corresponding severity level parameter. See
Message configuration on page 4-69.
Exclusive access into non-normal memory
LDREX, STREX and similar instructions are only guaranteed to operate correctly in normal memory.
Their operation in other memory types such as Device or Strongly Ordered, is not architecturally
defined and must not be relied on. For example, some implementations take an external abort.
BX or BLX to illegal addresses
An address ending 0b10 is not a legal branch target.
Non-normal pagetables should have XN bit set
The ARM architecture does not guarantee that a CPU executes instructions from non-normal
memory types such as Device or Strongly Ordered. Some implementations can take a pre-fetch
abort. It is recommended that the XN bit is set in pagetables for non-normal memory to avoid
seeing IMPLEMENTATION DEFINED effects in executed code.
Assumptions about cache geometry
Cache maintenance operations can be indexed by set and way. Any program that uses these
operations must have read the cache ID registers to determine the number of sets and ways
present in the system. Compatibility is not guaranteed if the target code attempts to infer this
information from reading the Main ID register.
Overlapping pagetable entries
It is an error if the TLB is allowed to contain more than one physical address mapping for each
combination of virtual address, Application Space Identifier (ASID) and security state. This
might occur if entries in the TLB are not flushed before loading a different set of pagetables
describing regions of a different size, or if pagetable entries are not correctly repeated for a
Supersection or Large Page entry.
Pagetable properties remapped whilst MMU is enabled
The status of System Control Register bits EE, AFE and TRE affect the way that pagetables are
interpreted, but it is IMPLEMENTATION DEFINED whether the interpretation takes place when the
TLB is loaded or when it is used. Therefore, if these bits are changed while there are active TLB
entries, any entries currently in the TLB might not be correctly interpreted.
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