Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
signalsGet() : uint8_t
Used by the master to get the current signal status. See Table 5-29 for bit
definitions.
Table 5-29 Bits for signalsGet()
Bits
Function
7:4 Reserved
3 DCD
2 DSR
1 CTS
0 RI
Parameters
Table 5-30 lists the parameters used by the PL011_Uart component.
Table 5-30 PL011_Uart configuration parameters
Parameter
name
Description
Type
Allowed
value
Default
value
clock_rate Clock rate for PL011. Integer - 14745600
baud_rate Baud rate. Integer - 38400
uart_enable
untimed_fifos a
Enables UART when
the system starts.
Controls the rate at
which serial data is
transferred between
the Tx/Rx FIFOs of
the UART and the
SerialData port.
Boolean true/false false
Boolean true/false false
a. When false, characters of serial data are clocked to/from the SerialData port at a rate
controlled by the clk_in_ref clock rate and the baud-rate-divider configuration of the
UART clock. Enabling untimed_fifos allows serial data to be sent/received as fast as it
can be generated/consumed. The modem control signals are still generated correctly, so
the UART is not able to transmit data faster than the receiving end can handle. (For
example, TelnetTerminal uses the CTS signal to avoid overflowing its TCP/IP buffer).
Registers
Table 5-31 gives a description of the configuration registers for the PL011_Uart component.
Table 5-31 PL011_Uart registers
Register
name
Offset Access Description
UARTDR 0x00 read/write Data register.
UARTRSR 0x04 read only Receive status register.
UARTECR 0x04 write only Error clear register.
ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-43
ID051811
Non-Confidential