Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components Ports Table 5-68 provides a brief description of the PL310_L2CC component ports. Refer to the component documentation for more details. Name Port protocol Type Description Table 5-68 PL310_L2CC ports pvbus_s PVBus Slave Slave port for connection to PV bus master/decoder pvbus_m PVBus Master Master port for connection to PV bus master/decoder DECERRINTR Signal Master Decode error received on master port from L3 ECNTRINTR Signal Master Event counter overflow / increment ERRRDINTR Signal Master Error on L2 data RAM read ERRRTINTR Signal Master Error on L2 tag RAM read ERRWDINTR Signal Master Error on L2 data RAM write ERRWTINTR Signal Master Error on L2 tag RAM write L2CCINTR Signal Master Combined interrupt output PARRDINTR Signal Master Parity error on L2 data RAM read PARRTINTR Signal Master Parity error on L2 tag RAM read SLVERRINTR Signal Master Slave error on master port from L3 Additional protocols The PL310_L2CC component has no additional protocols. Parameters Table 5-69 lists the parameters in the PL310_L2CC. Table 5-69 PL310_L2CC configuration parameters Parameter name Description Type Allowed value Default value ASSOCIATIVITY Associativity for auxiliary control register Integer 0 (8-way), 1 (16-way) 0 CACHEID cache-state_modelled a Cache controller cache ID Specifies whether real cache state is modeled (vs. register model) Integer 0 - 63 0 Boolean false/true false ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-87 ID051811 Non-Confidential
Peripheral and Interface Components Table 5-69 PL310_L2CC configuration parameters (continued) Parameter name Description Type Allowed value Default value CFGBIGEND Big-endian mode for accessing configuration registers out of reset Integer 0,1 0 LOCKDOWN_BY_LINE b Lockdown by line Integer 0,1 0 LOCKDOWN_BY_MASTER c Lockdown by master Integer 0,1 0 REGFILEBASE Base address for accessing configuration registers Integer 0 - 0xfffff000 0x1f002000 WAYSIZE Size of ways for auxiliary control register Integer 0 - 7 1 a. To understand the performance impact of enabling this parameter, see section Performance on page 5-90. b. Value is reflected in CacheType register bit 25, but the feature is not switched off when the parameter is 0. c. Value is reflected in CacheType register bit 26, but the feature is not switched off when the parameter is 0. Registers Table 5-70 provides a description of the configuration registers for the PL310_L2CC component. Table 5-70 PL310_L2CC registers Register name Offset Access Description CacheID 0x000 read only r0 cache ID CacheType 0x004 read only r0 cache type Ctrl 0x100 read/write r1 control AuxCtrl 0x104 read/write r1 auxiliary control TagLatencyCtrl a 0x108 read/write r1 tag RAM latency control DataLatencyCtrl a 0x10C write only r1 data RAM latency control EventCounterCtrl a 0x200 read/write r2 event counter control EventCounter1Cfg a 0x204 write only r2 event counter 1 configuration EventCounter0Cfg a 0x208 read/write r2 event counter0 configuration EventCounter1 a 0x20C read/write r2 event counter 1 value EventCounter0 a 0x210 read/write r2 event counter 0 value ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-88 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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