Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Table 5-89 SP810_SysCtrl registers (continued)
Register
name
Offset Access Description
SCITIR1 0xF08 read/write Integration test input 1
SCITOR 0xF0C read/write Integration test output
SCCNTCTRL 0xF10 read/write Counter test control
SCCNTDATA 0xF14 read/write Counter data
SCCNTSTEP 0xF18 write only Counter step
SCPeriphID0 0xFE0 read only Peripheral identification 0
SCPeriphID1 0xFE4 read only Peripheral identification 1
SCPeriphID2 0xFE8 read only Peripheral identification 2
SCPeriphID3 0xFEC read only Peripheral identification 3
SPCellID0 0xFF0 read only PrimeCell identification 0
SPCellID1 0xFF4 read only PrimeCell identification 1
SPCellID2 0xFF8 read only PrimeCell identification 2
SPCellID3 0xFFC read only PrimeCell identification 3
Debug features
The SP810_SysCtrl component has no debug features.
Verification and testing
The SP810_SysCtrl component has been tested as part of the Emulation Board model.
Performance
The SP810_SysCtrl component is not expected to significantly affect the performance of a PV
system.
Library dependencies
The SP810_SysCtrl component has no dependencies on external libraries.
5.4.29 TZIC component
The TZIC component is a programmer's view model of the TrustZone ® Interrupt Controller
(TZIC) as described elsewhere. See AMBA ® 3 TrustZone Interrupt Controller (SP890) Revision:
r0p0 Technical Overview (ARM DTO 0013).
The TZIC provides a software interface to the secure interrupt system in a TrustZone design. It
provides secure control of the nFIQ and masks out the interrupt sources chosen for nFIQ from
the interrupts that are passed onto a non-secure interrupt controller.
Figure 5-49 on page 5-116 shows a view of the component in System Canvas.
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