Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Table 5-76 PL350_SMC registers (continued)
Register name Offset Access Description
user_status 0x200 read/write User status register
user_config 0x204 read/write User configuration register
periph_id_0 0xFE0 read only Peripheral ID register 0 a
periph_id_1 0xFE4 read only Peripheral ID register 1 a
periph_id_2 0xFE8 read only Peripheral ID register 2 a
periph_id_3 0xFEC read only Peripheral ID register 3 a
pcell_id_0 0xFF0 read only PrimeCell ID register 0 a
pcell_id_1 0xFF4 read only PrimeCell ID register 1 a
pcell_id_2 0xFF8 read only PrimeCell ID register 2 a
pcell_id_3 0xFFC read only PrimeCell ID register 3 a
a. This register has no CADI interface.
Debug features
The PL350_SMC component has no debug features.
Verification and testing
The functions of the PL350_SMC component have been tested individually using a tailored test
suite.
Performance
The PL350_SMC component is optimized to have negligible impact on transaction
performance, except when memory remap settings are changed when there might be a
significant effect.
Library dependencies
The PL350_SMC component has no dependencies on external libraries.
5.4.24 PL350_SMC_NAND_FLASH component
The PL350_SMC_NAND_FLASH component is a programmer's view model of the flash that
must be connected to the PL350_SMC component. Information on how to program the
PL350_SMC_NAND_FLASH component is available in the component documentation. See
ARM PrimeCell Static Memory Controller (PL350 series) Technical Reference Manual.
Figure 5-44 shows a view of the component in System Canvas.
Figure 5-44 PL350_SMC_NAND_FLASH in System Canvas
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