Fast Models Reference Manual - ARM Information Center

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Chapter 2 Accuracy and Functionality This chapter describes the accuracy and functional scope of virtual platforms using models from Fast Models. It contains the following sections: • Model Capabilities Overview on page 2-2 • Functional caches in Fast Models on page 2-3 • How Accurate are Fast Models? on page 2-5 ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 2-1 ID051811 Non-Confidential
Accuracy and Functionality 2.1 Model Capabilities Overview Fast Models attempt to accurately model the hardware, but compromises exist between speed of execution, accuracy and other criteria. This means that a processor model may not be expected to match the hardware under certain conditions. For a detailed description of timing, bus and cache modelling limitations see Functional caches in Fast Models on page 2-3 and How Accurate are Fast Models? on page 2-5. 2.1.1 What Fast Models can do Fast Models do: • Instruction accurate modelling • Correct execution of well-written 1 code. 2.1.2 What Fast Models cannot do Fast Models cannot be used to: • Validate the hardware • Model unpredictable behavior • Model cycle counting • Model timing sensitive behavior • Model SMP instruction scheduling • Model software performance • Model bus traffic. 1. Well-written means “In accordance with the ARM Architecture Reference Manuals and the processor Technical Reference Manual”. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 2-2 ID051811 Non-Confidential
Page 1 and 2: Fast Models Version 6.1 Reference M
Page 3 and 4: Contents Fast Models Reference Manu
Page 5 and 6: Preface This preface introduces the
Page 7 and 8: Preface Typographical conventions T
Page 9 and 10: Preface Feedback ARM welcomes feedb
Page 11: Introduction 1.1 About the componen
Page 15 and 16: Accuracy and Functionality 2.2.2 Pe
Page 17 and 18: Accuracy and Functionality 2. For a
Page 19 and 20: Accuracy and Functionality Fast Mod
Page 21 and 22: Signaling and Clocking Protocols 3.
Page 23 and 24: Signaling and Clocking Protocols 3.
Page 25 and 26: Signaling and Clocking Protocols Pa
Page 27 and 28: Signaling and Clocking Protocols Ve
Page 29 and 30: Chapter 4 Processor Components This
Page 31 and 32: Processor Components 4.2 ARMCortexA
Page 33 and 34: Processor Components InstructionCou
Page 35 and 36: Processor Components c. This is a m
Page 39 and 40: Processor Components Table 4-4 ARMC
Page 43 and 44: Processor Components 4.3.9 Library
Page 47 and 48: Processor Components a. The ase-pre
Page 49 and 50: Processor Components 4.4.8 Performa
Page 51 and 52: Processor Components 4.5.3 Paramete
Page 53 and 54: Processor Components The debugger m
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Page 59 and 60: Processor Components 4.6.5 Caches T
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Processor Components Table 4-17 ARM
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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