Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
5.4.16 PL110_CLCD component
The PL110_CLCD component provides a programmer's view model of the PL110 Color LCD
(CLCD) controller PrimeCell. The model can be connected through a framebuffer port to, for
instance, a Visualisation component, so that LCD output can be viewed.
The implementation is intended to provide a register model of the LCD controller and both
timing and bus utilization models are made deliberately inaccurate to favor efficiency of
implementation and model speed.
Figure 5-35 shows a view of the component in System Canvas.
This component is written in LISA.
Figure 5-35 PL110_CLCD in System Canvas
Ports
Table 5-55 provides a brief description of the ports. See also the ARM PrimeCell Color LCD
Controller (PL110) Technical Reference Manual.
Name Port protocol Type Description
Table 5-55 PL110_CLCD ports
pvbus PVBus Slave Slave port for connection to PV bus
master/decoder.
intr Signal Master Interrupt signaling for flyback events.
clk_in ClockSignal Slave Master clock input, typically 24MHz, to
drive pixel clock timing.
display LCD Master Connection to visualization component.
See Visualization Library on
page 5-149.
control Value Slave Auxiliary control register 1.
pvbus_m PVBus Master DMA port for video data.
Additional protocols
The PL110_CLCD component has no additional protocols.
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