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Fast Models Reference Manual - ARM Information Center

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Processor Components<br />

4.12 <strong>ARM</strong>v7A - AEM<br />

The <strong>ARM</strong> Architecture Envelope Model (AEM) is a highly-configurable simulation model of a<br />

processor compliant to the <strong>ARM</strong>v7-A architecture supporting multiprocessor, large physical<br />

address and virtualization extensions. For information on characteristics and capabilities<br />

specific to the AEM, see Appendix A AEM <strong>ARM</strong>v7-A specifics.<br />

Figure 4-11 shows a view of the <strong>ARM</strong>AEMv7AMPCT model in the <strong>Fast</strong> <strong>Models</strong> Portfolio, with<br />

all vectored ports collapsed.<br />

This model is written in C++.<br />

Figure 4-11 <strong>ARM</strong>AEMv7AMPCT in System Canvas<br />

4.12.1 Ports<br />

Table 4-27 provides a brief description of the ports in the <strong>ARM</strong>AEMv7AMPCT model. Refer<br />

to the processor technical reference manual for more details.<br />

Name Port Protocol Type Description<br />

acp_s PVBus slave AXI ACP slave port<br />

Table 4-27 <strong>ARM</strong>AEMv7AMPCT ports<br />

cfgend[0-3] Signal slave Initialize to BE8 endianness after a<br />

reset.<br />

cfgnmfi[0-3] Signal slave Disables FIQ mask in CPSR.<br />

<strong>ARM</strong> DUI 0423J Copyright © 2008-2011 <strong>ARM</strong>. All rights reserved. 4-59<br />

ID051811<br />

Non-Confidential

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