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Peripheral and Interface Components
b. See PL080_DMAC_DmaPortProtocol on page 5-67.
Additional protocols
The PL022_SSP component has no additional protocols.
Parameters
The PL022_SSP component has no parameters.
Registers
Table 5-36 provides a description of the configuration registers for the PL022_SSP component.
Table 5-36 PL022_SSP registers
Register
name
Offset Access Description
SSPCR0 0x000 read/write Control register 0.
SSPCR1 0x004 read/write Control register 1.
SSPDR 0x008 read/write FIFO data.
SSPSR 0x00C read only Status.
SSPCPSR 0x010 read/write Clock prescale.
SSPIMSC 0x014 read/write Interrupt mask set/clear.
SSPRIS 0x018 read only Raw interrupt status.
SSPMIS 0x01C read only Masked interrupt status.
SSPICR 0x020 write only Interrupt clear.
SSPDMACR 0x024 read/write DMA control.
SSPeriphID0 0xFE0 read only Peripheral ID bits 7:0.
SSPeriphID1 0xFE4 read only Peripheral ID bits 15:8.
SSPeriphID2 0xFE8 read only Peripheral ID bits 23:16.
SSPeriphID3 0xFEC read only Peripheral ID bits 31:24.
SSPPCellID0 0xFF0 read only PrimeCell ID bits 7:0.
SSPPCellID01 0xFF4 read only PrimeCell ID bits 15:8.
SSPPCellID 0xFF8 read only PrimeCell ID bits 23:16.
SSPPCellID3 0xFFC read only PrimeCell ID bits 31:24.
Debug features
The PL022_SSP component has no debug features.
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