Fast Models Reference Manual - ARM Information Center

AEM ARMv7-A specifics
When the parameter vmsa.infinite_write_buffer is set, write accesses performed by one core
are not visible to other cores, or outside the processor, unless a relevant barrier operation is
performed or until a sufficiently long elapsed delay has occurred.
You can adjust the delay time with the parameter vmsa.write_buffer_delay, which is the
approximate number of instructions between successive buffer drains. If you set this parameter
to 0, then no time-based drains occur, and you must perform explicit barrier operations.
In regions marked as Device or Strongly Ordered memory, accesses complete in an order
relative to other accesses of the same type, but can be interleaved with accesses to Normal
memory. Writes to these regions are not combinable, and reads cannot be satisfied from the
buffer, so an explicit read access invokes the completion of all pending write accesses to that
memory type.
You can use this feature most effectively with the cache incoherence check. See Cache
incoherence check.
A.1.4
Treat cache invalidate operation as clean and invalidate
Rating: 1.
With the parameter vmsa.cache_treat_invalidate_as_clean set as true, a cache invalidate
operation cleans any dirty lines before they are invalidated.
Note
It is never appropriate to rely on incoherence effects of cached memory, because a cached view
can be cleaned or evicted at any time.
A.1.5
Cache incoherence check
Rating: 5.
When the parameter vmsa.cache_incoherence_check is set, the model warns about any data-side
memory read accesses whose result could have been ambiguous because of incoherency in the
system. The warning contains the physical address being accessed, and at least two data values
that could have been the result.
For example, consider an area of memory that has been copied into the Level 1 cache. If the
memory is changed by an external agent, then a read to these addresses could return either the
old value from the cache or the new value if that cache line is evicted.
Similar effects can occur in MP systems if newer values are pending in the writebuffer, or in a
writeback cache block outside the inner shared domain.
A.1.6
Delayed operation of CP15 instructions
Rating: 2.
In general, the functional effect of any operation in the system control co-processor, CP15 is not
guaranteed to occur until after an Instruction Synchronization Barrier (ISB) is subsequently
executed, or an exception entry or return occurs. There are several exceptions to this rule. Some
guarantee earlier visibility in certain circumstances, and others require extra steps to guarantee
that the operation takes place. These are described more fully in the ARM Architecture
Reference Manual ARMv7-A and ARMv7-R Edition.
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