Fast Models Reference Manual - ARM Information Center

Processor Components
Table 4-45 ARM926CT parameters (continued)
Parameter Description Type Values Default
dtcm0_size Size of DTCM in KB. integer 0x000 - 0x400 0x8
device-accurate-tlb
Specify whether all TLBs
are modeled.
boolean true/false false a
semihosting-cmd_line b
command line available to
semihosting SVC calls
string
no limit except
memory
[empty
string]
semihosting-debug c
semihosting-enable
enable debug output of
semihosting SVC calls
Enable semihosting SVC
traps.
Caution
Applications that do not
use semihosting must set
this parameter to false.
boolean true/false false
boolean true/false true
semihosting-ARM_SVC
semihosting-Thumb_SVC
ARM SVC number for
semihosting
Thumb SVC number for
semihosting
integer uint24_t 0x123456
integer uint8_t 0xAB
semihosting-heap_base virtual address of heap base integer 0x00000000 -
0xFFFFFFFF
0x0
semihosting-heap_limit
virtual address of top of
heap
integer 0x00000000 -
0xFFFFFFFF
0x0F000000
semihosting-stack_base
virtual address of base of
descending stack
integer 0x00000000 -
0xFFFFFFFF
0x10000000
semihosting-stack_limit
virtual address of stack
limit
integer 0x00000000 -
0xFFFFFFFF
0x0F0000000
a. Specifying false models enables modeling a different number of TLBs if this improves simulation
performance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy is
almost always sufficient. Specify true if device accuracy is required.
b. The value of argv[0] points to the first command line argument, not to the name of an image.
c. Currently ignored.
4.16.4 Registers
The ARM926CT component provides the registers specified by the technical reference manual
for the ARM926EJ-S with the following exceptions:
• coprocessor 14 registers are not implemented
• integration and test registers are not implemented.
4.16.5 Debug features
The ARM926CT component exports a CADI debug interface.
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