Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Table 5-31 PL011_Uart registers (continued)
Register
name
Offset Access Description
UARTFR 0x18 read only Flag register.
UARTILPR 0x20 read/write IrDA low-power counter a .
UARTIBRD 0x24 read/write Integer baud rate divisor.
UARTFBRD 0x28 read/write Fractional baud rate divisor.
UARTLCR_H 0x2C read/write Line control register, high
byte.
UARTCR 0x30 read/write Control register.
UARTFLS 0x34 read/write Interrupt FIFO level select.
UARTMSC 0x38 read/write Interrupt mask set/clear.
UARTRIS 0x3C read only Raw interrupt status.
UARTMIS 0x40 read only Masked interrupt register.
UARTICR 0x44 write only Interrupt clear register.
UARTDMACR 0x48 read/write DMA control register a .
a. Not implemented.
Debug features
The PL011_Uart component has no debug features.
Verification and testing
The PL011_Uart component has been tested as part of the VE example system using VE test
suites and by booting operating systems.
Performance
The PL011_Uart component is not expected to significantly affect the performance of a PV
system. However, at very high baud rates such as in excess of 1MHz, simulation performance
might be reduced.
Library dependencies
The PL011_Uart component has no dependencies on external libraries.
5.4.3 SerialCrossover component
The SerialCrossover component provides the functionality of a serial crossover cable. It
implements two SerialData slave ports and allows two SerialData master ports, such as from
PL011_Uart components, to be connected.
Data received on one port is buffered in a FIFO until it is read from the other port.
Signals received on one port are latched and available to be read by the other port.
Figure 5-22 on page 5-45 shows a view of the component in System Canvas.
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