Fast Models Reference Manual - ARM Information Center

Processor Components
b. Currently ignored.
4.8.4 Registers
The ARMCortexR5CT component provides the registers specified by the technical reference
manual for the Cortex-R5 with the following exceptions:
• coprocessor 14 registers are not implemented
• integration and test registers are not implemented.
4.8.5 Caches
The ARMCortexR5CT component implements L1 cache as architecturally defined, but does not
implement L2 cache.
4.8.6 Debug Features
The ARMCortexR5CT component exports a CADI debug interface.
Registers
All Core, VFP and CP15 registers, apart from performance counter registers, are visible in the
debugger. See the processor technical reference manual for a detailed description of available
registers.
The CP14 DSCR register is visible for compatibility reasons with some debuggers. This register
has no defined behavior.
Breakpoints
There is direct support for:
• single address unconditional instruction breakpoints
• unconditional instruction address range breakpoints
• single address unconditional data breakpoints.
The debugger might augment these with more complex combinations of breakpoints.
The current models support processor exception breakpoints by the use of pseudo-registers
available in the debugger register window. When debugger support is added to directly support
processor exceptions, these pseudo-registers will be removed.
Setting an exception register to a non-zero value will cause execution to stop on entry to the
associated exception vector.
Memory
The ARMCortexR5CT component presents a single 4GB view of memory.
4.8.7 Verification and Testing
The ARMCortexR5CT component has been tested using the architecture validation suite tests
for the ARM Cortex-R5.
4.8.8 Performance
The ARMCortexR5CT component provides high performance in all areas except VFP and
instruction set execution which currently does not use code translation technology.
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