Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components Ports Table 5-7 provides a brief description of the TZSwitch component ports. Name Port protocol Type Description Table 5-7 TZSwitch ports pvbus_input PVBus Slave Slave port for connection to PVBus master/decoder. pvbus_port_a PVBus Master Output port a. pvbus_port_b PVBus Master Output port b. control TZSwitchControl Slave Controls routing of transactions. TZSwitchControl The TZSwitch component has one additional protocol. routeAccesses (TZSwitch_InputFilter input, TZSwitch_RouteOption destination) : void Controls the routing of transactions on a TZSwitch component. Select the type of signals for reconfiguring by setting the value of input and destination. The possible values of input are: TZINPUT_SECURE changes the routing for secure transactions TZINPUT_NORMAL changes the routing for normal transactions TZINPUT_ANY changes the routing for all transactions. The possible values of destination are: TZROUTE_ABORT causes transactions to generate an abort TZROUTE_IGNORE causes transactions to be ignored, and reads return 0 TZROUTE_TO_PORT_A routes transactions to pvbus_port_a TZROUTE_TO_PORT_B routes transactions to pvbus_port_b. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-13 ID051811 Non-Confidential
Peripheral and Interface Components Parameters Table 5-8 lists the configuration parameters of the TZSwitch component. Table 5-8 TZSwitch configuration parameters Parameter name Description Type Allowed value Default value secure normal Default routing for secure transactions. Default routing for normal transactions. Integer 0, 1, 2, 3 1 Integer 0, 1, 2, 3 2 Note The secure and normal parameter values control the initial state of the TZSwitch component. Possible values for these parameters are: 0 ignore these transactions 1 forward the transactions to pvbus_port_a 2 forward the transactions to pvbus_port_b 3 generate an abort for these transactions. The numbers used for initial configuration are not the same as the enumeration constants used to control routing at runtime. Registers The TZSwitch component has no registers. Debug features The TZSwitch component has no debug features. Verification and testing The TZSwitch component has been tested as part of the VE example system using VE test suites and by booting operating systems. Performance The TZSwitch component is optimized to have negligible impact on transaction performance. Note When memory remap settings are changed when there might be a significant effect on performance. Library dependencies The TZSwitch component has no dependencies on external libraries. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-14 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components Table 4-13 ARM
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Glossary DSR DTR EB GIC GPIO I/O KM
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