Fast Models Reference Manual - ARM Information Center

Processor Components
Registers
All processor, CP15 registers are visible in the debugger. See the processor technical reference
manual for a detailed description of available registers.
The CP14 DSCR register is visible for compatibility reasons with some debuggers. This register
has no defined behavior.
Breakpoints
There is direct support for:
• single unconditional instruction breakpoints
• unconditional instruction range breakpoints
• single unconditional data breakpoints.
The debugger might augment these with more complex combinations of breakpoints. The
current models do not support processor exception breakpoints.
The current models support processor exception breakpoints by the use of pseudo-registers
available in the debugger register window. When debugger support is added to directly support
processor exceptions, these pseudo-registers are removed.
Setting an exception register to a non-zero value causes execution to stop on entry to the
associated exception vector.
Memory
The ARM926CT component presents a single flat 4GB view of virtual memory as seen by the
model processor.
4.16.6 Verification and testing
The ARM926CT component has been tested using
• the architecture validation suite tests for the ARM926EJ-S
• booting of Linux and Symbian on an example system containing an ARM926CT
component.
4.16.7 Performance
The ARM926CT component provides high performance in all areas.
4.16.8 Library dependencies
The ARM926CT component has no dependencies on external libraries.
4.16.9 Differences between the CT model and RTL implementations
The ARM926CT component differs from the corresponding revision of the ARM 926 RTL
implementation in the following ways:
• There is a single memory port combining instruction, data, DMA and peripheral access.
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