Fast Models Reference Manual - ARM Information Center

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Processor Components 4.15.9 Differences between the CT model and RTL implementations The ARM968CT component differs from the corresponding revision of the ARM 968 RTL implementation in the following ways: • No specific differences are listed. 4.15.10 DMA DMA to or from TCMs can be enabled by connecting the TCM ports to a standard PVBusDecoder. The ARM968CT or any other master can access the TCMs. The TCM regions do not behave exactly as described in the ARM968E-S TRM: • DTCM1 is not supported. • TCM memory does not alias throughout the 4MB TCM regions, only the lowest mapping can be used to access the TCMs. Aliasing can be implemented by appropriate mapping on the PVBusDecoder. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 4-84 ID051811 Non-Confidential
Processor Components 4.16 ARM926CT Figure 4-17 shows a view of the ARM926CT component in System Canvas. This component is based on r0p5 the ARM926EJ-S processor. This component is written in C++. Figure 4-17 ARM926CT in System Canvas 4.16.1 Ports Table 4-44 provides a brief description of the ports of the ARM926CT component. Refer to the processor technical reference manual for more details. Name Port protocol Type Description clk_in ClockSignal slave clock input Table 4-44 ARM926CT ports pvbus_m PVBus master master port for all memory accesses reset Signal slave asynchronous reset signal input irq Signal slave asynchronous IRQ signal input fiq Signal slave asynchronous FIQ signal input ticks InstructionCount master output that can be connected to a visualization component 4.16.2 Additional protocols The ARM926CT component has no additional protocols. 4.16.3 Parameters Table 4-45 provides a description of the configuration parameters for the ARM926CT component. Table 4-45 ARM926CT parameters Parameter Description Type Values Default BIGENDINIT INITRAM VINITHI initialize to ARMv5 big endian mode initialize with ITCM0 enabled at address 0x0 initialize with high vectors enabled boolean true/false false boolean true/false false boolean true/false false itcm0_size Size of ITCM in KB. integer 0x000 - 0x400 0x8 ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 4-85 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components 4.3 ARMCortexA
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Peripheral and Interface Components
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Versatile Express Model: Platform a
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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Fast Models Reference Manual - ARM Information Center

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