Fast Models Reference Manual - ARM Information Center

Signaling and Clocking Protocols
Verification and testing
The MasterClock component has been tested as part of the VE example system using VE test
suites and by booting operating systems.
Performance
The MasterClock component has no effect on the performance of a PV system.
Library dependencies
The MasterClock component has no dependencies on external libraries.
3.3.2 ClockDivider component
The ClockDivider component uses a configurable ratio to convert the ClockSignal rate at its
input to a new ClockSignal rate at its output. Changes to the input rate or ratio take effect
immediately and clocking components dependent on the output rate continue counting at the
new rate.
For examples of the use of ClockDividers, see the VEMotherBoard.lisa component in the
%PVLIB_HOME%\examples\RTSM_VE\LISA directory of your Fast Models distribution. On Linux, use
the $PVLIB_HOME/examples/RTSM_VE/LISA directory instead.
Figure 3-2 shows a view of the component in System Canvas.
This component is written in C++.
Figure 3-2 ClockDivider in System Canvas
Ports
Table 3-2 provides a brief description of the ClockDivider component ports.
Name Port protocol Type Description
clk_in ClockSignal slave source clock rate
clk_out ClockSignal master output clock rate
Table 3-2 ClockDivider ports
rate ClockRateControl slave allows the clock divider ratio to be
changed dynamically
ClockRateControl protocol
The ClockRateControl protocol can be used to set the ratio of a ClockDivider component.
set(uint32_t mul, uint32_t div) : void
sets the multiplier/divider that determines the clock divider ratio:
clk_out freq = clk_in freq * mul / div
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