Fast Models Reference Manual - ARM Information Center

Processor Components
Registers
All processor, VFP, CP14 and CP15 registers, apart from performance counter registers, are
visible in the debugger.
Breakpoints
There is direct support for:
• single address unconditional instruction breakpoints
• unconditional instruction address range breakpoints
• single address unconditional data breakpoints.
The debugger might augment these with more complex combinations of breakpoints.
The current models support processor exception breakpoints by the use of pseudo-registers
available in the debugger register window. When debugger support is added to directly support
processor exceptions, these pseudo-registers will be removed.
Setting an exception register to a non-zero value will cause execution to stop on entry to the
associated exception vector.
Memory
The Secure and Normal views show the contents of memory that are read by the core when it
performs a data-side memory access in the secure and non-secure modes in TrustZone. The
Level 1 cache is examined first, and in the case of a cache miss the Level 2 cache, if present, is
examined. This continues until external memory or peripherals are examined. This view is
indexed by modified virtual address.
The L1-DCache, L1-DCacheNS, L2-DCache, ... views show the contents of an individual cache
block. If there is a cache miss at this level, no data is shown. These views cause no side-effects
in the simulation. This view is indexed by physical address.
The External and ExternalNS views show the contents of memory available from the external
bus interface of the processor. Memory is shown only if it can be read without causing side
effects. In most cases, the contents of the RAM are available but peripheral registers are not.
Availability of non-idempotent memory such as flash units might depend on the state of the flash
unit and code that has already been executed in the model. This view is indexed by physical
address.
TLB
Each active core in the processor exports a CADI interface that describes the current contents
of its TLB.
Note
This view is subject to change in future versions.
You can examine TLB entries by opening a Disassembly view in the debugger window for the
TLB CADI interface. You can select two display modes from the Memory Space menus:
• Entries by index
• Entries by MVA on page 4-71.
Entries by index
The Address field is an index into a linear, ordered list of TLB entries.
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