Fast Models Reference Manual - ARM Information Center

Processor Components
The debugger might augment these with more complex combinations of breakpoints.
The current models support processor exception breakpoints by the use of pseudo-registers
available in the debugger register window. When debugger support is added to directly support
processor exceptions, these pseudo-registers are removed.
Setting an exception register to a non-zero value causes execution to stop on entry to the
associated exception vector.
Memory
The ARMCortexA8CT component presents two 4GB views of virtual memory, one as seen
from secure mode and one as seen from normal mode.
4.5.7 Verification and testing
The ARMCortexA8CT component has been tested using:
• the architecture validation suite tests for the ARM Cortex-A8 processor
• booting of Linux, Symbian and Windows CE on an example system containing an
ARMCortexA8CT component.
4.5.8 Performance
The ARMCortexA8CT component provides high performance in all areas except VFP and
NEON instruction set execution which currently does not use code translation technology.
4.5.9 Library dependencies
The ARMCortexA8CT component has no dependencies on external libraries.
4.5.10 Differences between the CT model and RTL implementations
The ARMCortexA8CT component differs from the corresponding revision of the ARM
Cortex-A8 RTL implementation in the following ways:
• There is a single memory port combining instruction, data, DMA and peripheral access.
• ARMCortexA8CT L2 cache write allocate policy is not configurable. It defaults to
write-allocate. Writes to the configuration register succeed but are ignored, meaning that
data can be unexpectedly stored in the L2 cache.
• Unaligned accesses with the MMU disabled on the ARMCortexA8CT do not cause data
aborts.
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