Fast Models Reference Manual - ARM Information Center

Processor Components
Name Port Protocol Type Description
Table 4-18 ARMCortexR5CT ports (continued)
groupid Value Slave Group ID used for MPIDR.
initrama[2] Signal Slave If ATCM is enabled at reset.
initramb[2] Signal Slave If BTCM is enabled at reset.
irq[2] Signal Slave This signal drives the interrupt handling
of the CPU.
loczrama[2] Signal Slave Location of ATCM at reset.
pmuirq[2] Signal Master Interrupt signal from performance
monitoring unit.
pvbus_m PVBus Master The processor generates bus requests on
this port.
reset[2] Signal Slave Raising this signal puts the processor into
reset mode.
slreset Signal Slave Split lock signal. Contact ARM for
details.
slsplit Signal Slave Split lock signal. Contact ARM for
details.
standbywfe[2] Signal Master This signal indicates if a processor is in
wfe state.
standbywfi[2] Signal Master This signal indicates if a processor is in
WFI state.
teinit[2] Signal Slave Default exception handling state.
ticks[2] InstructionCount Master Connect this port to one of the two ticks
ports on a visualization component to
display a running instruction count.
vic_ack[2] Signal Master Vic acknowledge port to primary VIC.
vic_addr[2] ValueState Slave Vic address port from primary VIC.
vinithi Signal Slave This signal controls the location of the
exception vectors at reset.
4.8.2 Additional Protocols
The ARMCortexR5CT component has one additional protocol.
InstructionCount
The InstructionCount protocol has one behavior.
getValue
Obtain the number of instructions executed by the processor.
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