Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components Table 5-67 PL192_VIC registers (continued) Register name Offset Access Description INTENABLE 0x010 read/write Interrupt enable register INTENCLEAR 0x014 write only Interrupt enable clear register SOFTINT 0x018 read/write Software interrupt register SOFTINTCLEAR 0x01C write only Software interrupt clear register PROTECTION 0x020 read/write Protection enable register SWPRIORITY 0x024 read/write Software priority mask PRIORITYDAISY 0x028 read/write Vector priority register for daisy chain VECTADDR[0:31] 0x100 - 0x17C VECTPRIORITY[0:31] 0x200 - 0x27C read/write read/write 32 vector addresses 32 priority registers VICADDRESS 0xF00 read/write Vector address register Debug features The PL192_VIC component has no debug features. Verification and testing The PL192_VIC has been run against the RTL validation suite and has been successfully used in validation platforms. Performance The PL192_VIC component is not expected to significantly affect the performance of a PV system. Library dependencies The PL192_VIC component has no dependencies on external libraries. 5.4.21 PL310_L2CC component The PL310_L2CC provides a model of an Level 2 Cache Controller (L2CC). The presence of additional on-chip secondary cache can improve performance when significant memory traffic is generated by the processor. A secondary cache assumes the existence of a Level 1, or primary, cache, which is closely coupled or internal to the processor. For more information, refer to the component documentation. See the ARM PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual. For more information about the accuracy and functionality of Fast Models and cache models see Chapter 2 Accuracy and Functionality. The PL310_L2CC component has two modes of operation • Register view: Cache control registers are present but the cache behavior is not modeled. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-85 ID051811 Non-Confidential
Peripheral and Interface Components • Functional model: Cache behavior is modeled. The mode of operation is controlled by a parameter to the component. See Parameters on page 5-87, parameter cache-state_modelled. Figure 5-40 shows a view of the component in System Canvas. This component is written in LISA+. Figure 5-40 PL310_L2CC in System Canvas The PL310 is only supported when connected to the Cortex-A5 or Cortex-A9 processor. An example system is shown in Figure 5-41. Figure 5-41 PL310_L2CC in an example system ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-86 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Versatile Express Model: Platform a
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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Fast Models Reference Manual - ARM Information Center

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