Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Registers
Table 5-91 provides a description of the configuration registers for the TZIC component.
Register name Offset Access Description
Table 5-91 TZIC registers
FIQStatus 0x000 read only Provide the status of the
interrupts after FIQ
masking.
RawIntr 0x004 read only Provide the status of the
source interrupts and
software interrupts to the
interrupt controller.
IntSelect 0x008 read/write Select whether the
corresponding input source
can be used to generate an
FIQ or whether it passes
through to TZICIRQOUT.
FIQEnable 0x00C read/write Enable the corresponding
FIQ-selected input source,
which can then generate an
FIQ.
FIQEnClear 0x010 write only Clear bits in the
TZICFIQEnable register.
Bypass 0x014 read/write Enable nNSFIQIN to be
routed directly to FAQ,
bypassing all TZIC logic.
Only the least significant bit
is used.
Protection 0x018 read/write Enable or disable protected
register access, stopping
register accesses when the
processor is in user mode.
Lock 0x01C write only Enable or disable all other
register write access.
LockStatus 0x020 read only Provide the lock status of
the TZIC registers.
Debug features
The TZIC component has no debug features.
Verification and testing
The TZIC component has been tested separately using its own test suite.
The SP890 TZIC component has been tested inside the SMLT component.
The FIQ has been tested under the secure environment.
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