Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components Registers Table 5-42 provides a description of the registers for the PL041_AACI component. Table 5-42 PL041_AACI registers Register name Offset Access Description RXCR1 0x00 read/write FIFO1 receive control TXCR1 0x04 read/write FIFO1 transmit control SR1 0x08 read/write Channel 1 status ISR1 0x0C read/write Channel 1 interrupt status IE1 0x10 read/write Channel 1 interrupt enable RXCR2 0x14 read/write FIFO2 receive control TXCR2 0x18 read/write FIFO2 transmit control SR2 0x1C read/write Channel 2 status ISR2 0x20 read/write Channel 2 interrupt status IE2 0x24 read/write Channel 2 interrupt enable RXCR3 0x28 read/write FIFO3 receive control TXCR3 0x2C read/write FIFO3 transmit control SR3 0x30 read/write Channel 3 status ISR3 0x34 read/write Channel 3 interrupt status IE3 0x38 read/write Channel 3 interrupt enable RXCR4 0x3C read/write FIFO4 receive control TXCR4 0x40 read/write FIFO4 transmit control SR4 0x44 read/write Channel 4 status ISR4 0x48 read/write Channel 4 interrupt status IE4 0x4C read/write Channel 4 interrupt enable SL1RX 0x50 read/write Slot 1 receive data SL1TX 0x54 read/write Slot 1 transmit data SL2RX 0x58 read/write Slot 2 receive data SL2TX 0x5C read/write Slot 2 transmit data SL12RX 0x60 read/write Slot 12 receive data SL12TX 0x64 read/write Slot 12 transmit data LSFR 0x68 read/write Slot flag register SLISTAT 0x6C read/write Slot interrupt status SLIEN 0x70 read/write Slot interrupt enable ALLINTCLR 0x74 write only All interrupts clear ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-55 ID051811 Non-Confidential
Peripheral and Interface Components Table 5-42 PL041_AACI registers (continued) Register name Offset Access Description MAINCR 0x78 read/write Main control RESET 0x7C read/write Reset control SYNC 0x80 read/write Sync control ALLINTS 0x84 read/write All FIFO interrupts status MAINFR 0x88 read/write Main flags register Debug features The PL041_AACI component has no debug features. Verification and testing The PL041_AACI component has been tested using the ALSA driver for this component under Linux. Performance The PL041_AACI component relies on a timed callback from the simulation so might have a small impact on simulation performance. The ability to play audio through this component depends on the AudioOut Component in use and on the performance requirements of the software running on the simulated system. The rate of FIFO draining is controlled by the audio output to which the component is connected. This might not correspond to the rate that would be expected from the reference clock. Library dependencies The PL041_AACI component has no dependencies on external libraries. 5.4.9 AudioOut_File component The AudioOut_File component implements and audio output suitable for use with the PL041_AACI component. It writes raw 16 bit 48KHz stereo audio data to a user specified file. Figure 5-28 shows a view of the component in System Canvas. This component is written in LISA+. Figure 5-28 AudioOut in System Canvas ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-56 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Versatile Express Model: Platform a
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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