Fast Models Reference Manual - ARM Information Center

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Processor Components Table 4-41 ARM1136CT parameters (continued) Parameter Description Type Values Default semihosting-stack_limit virtual address of stack limit integer 0x00000000 - 0xFFFFFFFF 0x0F0000000 vfp-enable_at_reset d enable coprocessor access and VFP at reset boolean true/false false vfp-present configure processor as VFP boolean true/false true enabled e a. Specifying false models enables modeling a different number of TLBs if this improves simulation performance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy is almost always sufficient. Specify true if device accuracy is required. b. The value of argv[0] points to the first command line argument, not to the name of an image. c. Currently ignored. d. This is model specific behavior with no hardware equivalent. e. This parameter lets you disable the VFP features of the model. However the model has not been validated as a true ARM1136J-S processor. 4.14.4 Registers The ARM1136CT component provides the registers specified by the technical reference manual for the ARM1136JF-S with the following exceptions: • coprocessor 14 registers are not implemented • integration and test registers are not implemented. 4.14.5 Debug features The ARM1136CT component exports a CADI debug interface. Registers All processor, VFP and CP15 registers, apart from performance counter registers, are visible in the debugger. See the processor technical reference manual for a detailed description of available registers. The CP14 DSCR register is visible for compatibility reasons with some debuggers. This register has no defined behavior. Breakpoints There is direct support for: • single unconditional instruction breakpoints • unconditional instruction range breakpoints • single unconditional data breakpoints. The debugger might augment these with more complex combinations of breakpoints. The current models support processor exception breakpoints by the use of pseudo-registers available in the debugger register window. When debugger support is added to directly support processor exceptions, these pseudo-registers are removed. Setting an exception register to a non-zero value causes execution to stop on entry to the associated exception vector. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 4-78 ID051811 Non-Confidential
Processor Components Memory The ARM1136CT component presents a single flat 4GB view of virtual memory as seen by the model processor. 4.14.6 Verification and testing The ARM1136CT component has been tested using: • the architecture validation suite tests for the ARM1136JZF-S • booting of Linux and other operating systems on an example system containing an ARM1136CT component. 4.14.7 Performance The ARM1136CT component provides high performance in all areas except VFP instruction set execution which currently does not use code translation technology. 4.14.8 Library dependencies The ARM1136CT component has no dependencies on external libraries. 4.14.9 Differences between the CT model and RTL implementations The ARM1136CT component differs from the corresponding revision of the ARM 1136 RTL implementation in the following ways: • There is a single memory port combining instruction, data, DMA and peripheral access. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 4-79 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components 4.3 ARMCortexA
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Peripheral and Interface Components
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Versatile Express Model: Platform a
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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