Fast Models Reference Manual - ARM Information Center

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Microcontroller Prototyping System: Platform and Components 8.2 MPS model memory map This section describes the MPS memory map. For standard ARM peripherals, see the TRM for that device. Table 8-1 Overview of MPS memory map Description Modeled Address range 4MB Remap region for SRAM0 overlay of Flash Yes 0x00000000–0x003FFFFF Non remapped Flash memory Yes 0x00400000–0x03FFFFFF SRAM for code and data storage (remap RAM) Yes 0x10000000–0x103FFFFF SRAM for code and data storage Yes 0x10400000–0x107FFFFF FLASH aliased for programming Yes 0x18000000–0x1BFFFFFF CPU System Registers Yes 0x1F000000–0x1F000FFF Reserved for SMC configuration registers N/A 0x1F001000–0x1F002FFF I2C for DVI Yes 0x1F003000–0x1F003FFF PL022 SPI for Touch Screen Yes 0x1F004000–0x1F004FFF PL011 UART Yes 0x1F005000–0x1F005FFF Reserved N/A 0x1F006000–0x1FFFFFFF SP805 Watch Dog Yes 0x40000000–0x4000FFFF PL031 RTC Yes 0x40001000–0x40001FFF SP804 Timer (0) Yes 0x40002000–0x40002FFF SP804 Timer (1) Yes 0x40003000–0x40003FFF DUT Sys Regs Yes 0x40004000–0x40004FFF PL181 SD/MMC controller Yes 0x40005000–0x40005FFF Reserved N/A 0x40006000–0x40006FFF PL011 UART (1) Yes 0x40007000–0x40007FFF PL011 UART (2) Yes 0x40008000–0x40008FFF PL011 UART (3) Yes 0x40009000–0x40009FFF PL041 AC97 controller Yes 0x4000A000–0x4000AFFF DS702 I2C (ADCDAC) Partial a 0x4000B000–0x4000BFFF DUT Character LCD Yes 0x4000C000–0x4000CFFF Reserved N/A 0x4000D000–0x4000EFFF Reserved N/A 0x4FFA0000–0x4FFAFFFF Flexray Partial a 0x4FFB0000–0x4FFBFFFF CAN Partial a 0x4FFC0000–0x4FFCFFFF ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 8-3 ID051811 Non-Confidential
Microcontroller Prototyping System: Platform and Components Table 8-1 Overview of MPS memory map (continued) Description Modeled Address range LIN Partial a 0x4FFD0000–0x4FFDFFFF Ethernet Partial a 0x4FFE0000–0x4FFEFFFF Video Yes 0x4FFF0000–0x4FFFFFFF External AHB interface to DUT FPGA Yes 0x50000000–0x5FFFFFFF DMC Yes 0x60000000–0x9FFFFFFF SMC Yes 0xA0000000–0xAFFFFFFF Private Peripheral Bus Yes 0xE0000000–0xE00FFFFF System bus interface to DUT FPGA Yes 0xE0100000–0xFFFFFFFF a. This model is represented by a register bank and has no functionality beyond this. Note A Bus Error is generated for accesses to memory areas not shown above. Any memory device that does not occupy the total region is aliased within that region. 8.2.1 MPS registers This section describes the MPS memory-mapped registers. CPU system registers Table 8-2 provides a description of the CPU system registers. Table 8-2 MPS CPU system registers Register name Address Access Description SYS_ID 0x1F000000 read/write Board and FPGA identifier SYS_MEMCFG 0x1F000004 read/write Memory remap and alias SYS_SW 0x1F000008 read/write Indicates user switch settings SYS_LED 0x1F00000C read/write Sets LED outputs SYS_TS 0x1F000010 read/write TouchScreen register ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 8-4 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Page 293 and 294: Versatile Express Model: Platform a
Page 313 and 314: Chapter 7 Emulation Baseboard Model
Page 315 and 316: Emulation Baseboard Model: Platform
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Page 355 and 356: AEM ARMv7-A specifics A.1 Boundary
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Page 363 and 364: AEM ARMv7-A specifics A.3 IMPLEMENT
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Page 367 and 368: Glossary DSR DTR EB GIC GPIO I/O KM
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