Fast Models Reference Manual - ARM Information Center

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Signaling and Clocking Protocols 3.2 Signaling Protocols This section describes the common signaling protocols within the Fast Models Portfolio. It contains the following sections: • Signal protocol • StateSignal protocol • Value protocol • ValueState protocol. 3.2.1 Signal protocol The Signal protocol has the following behavior: setValue(enum sg::Signal::State) : void indicates a state change. Legal values for sg::Signal::State are: • sg::Signal::Set • sg::Signal::Clear 3.2.2 StateSignal protocol The StateSignal protocol has two behaviors: setValue(enum sg::Signal::State) : void indicates a value change getValue() : sg::Signal::State reads the current value. 3.2.3 Value protocol The Value protocol has the following behavior: setValue(uint32_t value) indicates a state change. 3.2.4 ValueState protocol The ValueState protocol has the following behaviors: setValue(uint32_t value) : void indicates a value change getValue() : uint32_t read the current value state. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 3-3 ID051811 Non-Confidential
Signaling and Clocking Protocols 3.3 Clocking components and protocols This section describes the common clocking components and protocols within Fast Models. It contains the following sections: • MasterClock component • ClockDivider component on page 3-5 • ClockTimer component on page 3-6. 3.3.1 MasterClock component The MasterClock component provides a single ClockSignal output that can be used to drive the ClockSignal input of ClockDividers, ClockTimers and other clocking components. The rate of the MasterClock is not defined because all clocking is relative, but can be considered to be 1Hz. A system may contain more than one MasterClock, all of which generate the same ClockSignal rate. Figure 3-1 shows a view of the component in System Canvas. This component is written in C++. Figure 3-1 MasterClock in System Canvas Ports Table 3-1 provides a brief description of the ports. Refer to the component documentation for more details. Name Port protocol Type Description clk_out ClockSignal master master clock rate Table 3-1 MasterClock ports Additional protocols The MasterClock component has no additional protocols. Parameters The MasterClock component has no parameters. Registers The MasterClock component has no registers. Debug features The MasterClock component has no debug features. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 3-4 ID051811 Non-Confidential
Page 1 and 2: Fast Models Version 6.1 Reference M
Page 3 and 4: Contents Fast Models Reference Manu
Page 5 and 6: Preface This preface introduces the
Page 7 and 8: Preface Typographical conventions T
Page 9 and 10: Preface Feedback ARM welcomes feedb
Page 11 and 12: Introduction 1.1 About the componen
Page 13 and 14: Accuracy and Functionality 2.1 Mode
Page 15 and 16: Accuracy and Functionality 2.2.2 Pe
Page 17 and 18: Accuracy and Functionality 2. For a
Page 19 and 20: Accuracy and Functionality Fast Mod
Page 21: Signaling and Clocking Protocols 3.
Page 25 and 26: Signaling and Clocking Protocols Pa
Page 27 and 28: Signaling and Clocking Protocols Ve
Page 29 and 30: Chapter 4 Processor Components This
Page 31 and 32: Processor Components 4.2 ARMCortexA
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Chapter 7 Emulation Baseboard Model
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Glossary DSR DTR EB GIC GPIO I/O KM
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