Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Ports
Table 5-96 provides a brief description of the ports for the BP135_AXI2APB component. Refer
to the component documentation for more details.
Name Port protocol Type Description
Table 5-96 BP135_AXI2APB ports
AXI PVBus Slave Slave port for connection to a PVBus
master/decoder
P0 - P15 PVBus Master Master ports for connection to PVBus
slaves
TZPROT0
TZPROT1
Value Slave Control ports for selecting secure state
of slaves
Additional protocols
The BP135_AXI2APB component has no additional protocols.
Parameters
The BP135_AXI2APB component has no parameters.
Registers
The BP135_AXI2APB component has no registers.
Debug features
The BP135_AXI2APB component has no debug features.
Verification and testing
The BP135_AXI2APB component has been tested as part of an integrated platform.
Performance
The BP135_AXI2APB component should not significantly impact performance of a PV system.
Library dependencies
The BP135_AXI2APB component is dependent on the BP135TZSwitchControl component
which is used to decode the protection selection bits provided by the TZPROT ports and control
the protection routing of the embedded TZSwitch routing components. See TZSwitch
component on page 5-12.
5.4.33 BP141_TZMA component
The BP141_TZMA component provides a Programmer’s View of the BP141 TrustZone
Memory Adapter (TZMA). This allows a single physical memory cell of up to 2MB to be shared
between a secure and non-secure storage area. The partitioning between these areas is flexible.
The BP141_TZMA routes transactions according to:
• the memory region that they are attempting to access
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