Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Table 5-54 PL080_DMAC registers (continued)
Register name Offset Access Description
SoftLSReq 0x02C read/write Soft last single
request/status
Configuration 0x030 read/write Master configuration
Sync 0x034 read/write Synchronization control
C0SrcAddr 0x100 read/write Channel source address
C0DstAddr 0x104 read/write Channel destination address
C0LLI 0x108 read/write Channel linked list item
C0Control 0x10C read/write Channel control
C0Config 0x110 read/write Channel configuration
C1SrcAddr 0x120 read/write Channel source address
C1DstAddr 0x124 read/write Channel destination address
C1LLI 0x128 read/write Channel linked list item
C1Control 0x12C read/write Channel control
C1Config 0x130 read/write Channel configuration
C2SrcAddr 0x140 read/write Channel source address
C2DstAddr 0x144 read/write Channel destination address
C2LLI 0x148 read/write Channel linked list item
C2Control 0x14C read/write Channel control
C2Config 0x150 read/write Channel configuration
C3SrcAddr 0x160 read/write Channel source address
C3DstAddr 0x164 read/write Channel destination address
C3LLI 0x168 read/write Channel linked list item
C3Control 0x16C read/write Channel control
C3Config 0x170 read/write Channel configuration
C4SrcAddr 0x180 read/write Channel source address
C4DstAddr 0x184 read/write Channel destination address
C4LLI 0x188 read/write Channel linked list item
C4Control 0x18C read/write Channel control
C4Config 0x190 read/write Channel configuration
C5SrcAddr 0x1A0 read/write Channel source address
C5DstAddr 0x1A4 read/write Channel destination address
C5LLI 0x1A8 read/write Channel linked list item
C5Control 0x1AC read/write Channel control
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