Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Table 5-54 PL080_DMAC registers (continued)
Register name Offset Access Description
C5Config 0x1B0 read/write Channel configuration
C6SrcAddr 0x1C0 read/write Channel source address
C6DstAddr 0x1C4 read/write Channel destination address
C6LLI 0x1C8 read/write Channel linked list item
C6Control 0x1CC read/write Channel control
C6Config 0x1D0 read/write Channel configuration
C7SrcAddr 0x1E0 read/write Channel source address
C7DstAddr 0x1E4 read/write Channel destination address
C7LLI 0x1E8 read/write Channel linked list item
C7Control 0x1EC read/write Channel control
C7Config 0x1F0 read/write Channel configuration
PeriphID0 0xFE0 read only PrimeCell peripheral ID
PeriphID1 0xFE4 read only PrimeCell peripheral ID
PeriphID2 0xFE8 read only PrimeCell peripheral ID
PeriphID3 0xFEC read only PrimeCell peripheral ID
PCellID0 0xFF0 read only PrimeCell ID
PCellID1 0xFF4 read only PrimeCell ID
PCellID2 0xFF8 read only PrimeCell ID
PCellID3 0xFFC read only PrimeCell ID
Debug features
The PL080_DMAC component has no debug features.
Verification and testing
The functions of the PL080_DMAC component have been tested individually using a tailored
test suite.
Performance
The PL080_DMAC component might have a significant impact on system performance in
certain flow control modes. Channels configured for small bursts, or using single bursts, and
with peripheral DMA handshaking could add significant overheads. The peripheral has not been
fully optimized to make use of the advanced features of the PVBus model.
Library dependencies
The PL080_DMAC component has no dependencies on external libraries.
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