Fast Models Reference Manual - ARM Information Center

Processor Components
4.16 ARM926CT
Figure 4-17 shows a view of the ARM926CT component in System Canvas. This component is
based on r0p5 the ARM926EJ-S processor.
This component is written in C++.
Figure 4-17 ARM926CT in System Canvas
4.16.1 Ports
Table 4-44 provides a brief description of the ports of the ARM926CT component. Refer to the
processor technical reference manual for more details.
Name Port protocol Type Description
clk_in ClockSignal slave clock input
Table 4-44 ARM926CT ports
pvbus_m PVBus master master port for all memory accesses
reset Signal slave asynchronous reset signal input
irq Signal slave asynchronous IRQ signal input
fiq Signal slave asynchronous FIQ signal input
ticks InstructionCount master output that can be connected to a
visualization component
4.16.2 Additional protocols
The ARM926CT component has no additional protocols.
4.16.3 Parameters
Table 4-45 provides a description of the configuration parameters for the ARM926CT
component.
Table 4-45 ARM926CT parameters
Parameter Description Type Values Default
BIGENDINIT
INITRAM
VINITHI
initialize to ARMv5 big
endian mode
initialize with ITCM0
enabled at address 0x0
initialize with high vectors
enabled
boolean true/false false
boolean true/false false
boolean true/false false
itcm0_size Size of ITCM in KB. integer 0x000 - 0x400 0x8
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