Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components Table 5-89 SP810_SysCtrl registers (continued) Register name Offset Access Description SCITIR1 0xF08 read/write Integration test input 1 SCITOR 0xF0C read/write Integration test output SCCNTCTRL 0xF10 read/write Counter test control SCCNTDATA 0xF14 read/write Counter data SCCNTSTEP 0xF18 write only Counter step SCPeriphID0 0xFE0 read only Peripheral identification 0 SCPeriphID1 0xFE4 read only Peripheral identification 1 SCPeriphID2 0xFE8 read only Peripheral identification 2 SCPeriphID3 0xFEC read only Peripheral identification 3 SPCellID0 0xFF0 read only PrimeCell identification 0 SPCellID1 0xFF4 read only PrimeCell identification 1 SPCellID2 0xFF8 read only PrimeCell identification 2 SPCellID3 0xFFC read only PrimeCell identification 3 Debug features The SP810_SysCtrl component has no debug features. Verification and testing The SP810_SysCtrl component has been tested as part of the Emulation Board model. Performance The SP810_SysCtrl component is not expected to significantly affect the performance of a PV system. Library dependencies The SP810_SysCtrl component has no dependencies on external libraries. 5.4.29 TZIC component The TZIC component is a programmer's view model of the TrustZone ® Interrupt Controller (TZIC) as described elsewhere. See AMBA ® 3 TrustZone Interrupt Controller (SP890) Revision: r0p0 Technical Overview (ARM DTO 0013). The TZIC provides a software interface to the secure interrupt system in a TrustZone design. It provides secure control of the nFIQ and masks out the interrupt sources chosen for nFIQ from the interrupts that are passed onto a non-secure interrupt controller. Figure 5-49 on page 5-116 shows a view of the component in System Canvas. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-115 ID051811 Non-Confidential
Peripheral and Interface Components Figure 5-49 TZIC in System Canvas This component is written in LISA+. Ports Table 5-90 provides a brief description of the ports. More details are in the Technical Overview. See the AMBA ® 3 TrustZone Interrupt Controller (SP890) Revision: r0p0 Technical Overview. Name Port protocol Type Description Table 5-90 TZIC ports nsfiq_in Signal Slave Connects to the nFIQ output of the non-secure interrupt controller pvbus PVBus Slave Slave port for connection to PV bus master/decoder sfiq_in Signal Slave Daisy chaining secure FIQ input, otherwise connects to logic 1 if interrupt controller not daisy chained input[32] Signal Slave 32 interrupt input sources fiq_out Signal Master Fast interrupt request to processor irq_out[32] Signal Master 32 IRQ output ports Additional protocols The TZIC component has no additional protocols. Parameters The TZIC component has no parameters. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-116 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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