Verifikation reaktiver Systeme - Universität Kaiserslautern

231
REG (x)
REG (y)
COUNTER (k)
n
0
n
0
>>1
>>1
1 0
1 0
A−B
Abool, out:num->bool) =
!t. out t = ~inp t‘;
val OR_def = Define ‘OR(in1:num->bool,in2:num->bool,out:num->bool) =
!t. out t = (in1 t) \/ (in2 t)‘;
val AND_def = Define ‘AND(in1:num->bool,in2:num->bool,out:num->bool) =
!t. out t = (in1 t) /\ (in2 t)‘;
val MUX_def = Define
‘MUX(sw:num->bool,in1:num->num,in2:num->num,out:num->num) =
!t. out t = if sw t then in1 t else in2 t‘;
val COUNTER_def = Define ‘COUNTER(inp:num->bool,out:num->num) =
!t. out t = if (t=0) then 0 else
if (inp t) then (out(t-1)+1) else out(t-1)‘;
val REG_def = Define ‘REG(inp:num->num,out:num->num,init:num) =
!t. out t = if (t=0) then init else inp (t-1)‘;