Cortex-A8 Technical Reference Manual - ARM Information Center

3.2.7 c0, Processor Feature Register 0
3.2.8 c0, Processor Feature Register 1
System Control Coprocessor
The purpose of Processor Feature Register 0 is to provide information about the execution state
support and programmer’s model for the processor.
The Processor Feature Register 0 is:
• a read-only register common to the Secure and Nonsecure states
• accessible in privileged modes only.
Figure 3-4 shows the bit arrangement of the Processor Feature Register 0.
31 16 15 12 11 8 7 4 3 0
Reserved
Figure 3-4 Processor Feature Register 0 format
Table 3-12 shows how the bit values correspond with the Processor Feature Register 0
functions.
Bits Field Function
[31:16] - Reserved, RAZ.
Table 3-13 shows the results of attempted access for each mode.
To access the Processor Feature Register 0, read CP15 with:
MRC p15, 0, , c0, c1, 0 ; Read Processor Feature Register 0
The purpose of Processor Feature Register 1 is to provide information about the execution state
support and programmer’s model for the processor.
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State3
State2 State1 State0
Table 3-12 Processor Feature Register 0 bit functions
[15:12] State3 Indicates support for Thumb Execution Environment (ThumbEE):
0x1 = Processor supports ThumbEE.
[11:8] State2 Indicates support for Jazelle extension interface:
0x1 = Jazelle extension supported.
[7:4] State1 Indicates the type of Thumb encoding that the processor supports:
0x3 = Processor supports Thumb-2 encoding with all Thumb-2 instructions.
[3:0] State0 Indicates support for ARM instruction set:
0x1 = Processor supports ARM instructions.
Table 3-13 Results of access to the Processor Feature Register 0 a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Data Undefined Data Undefined Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.