Cortex-A8 Technical Reference Manual - ARM Information Center

3.2.22 c0, Silicon ID Register
System Control Coprocessor
31 30 29 27 26 24 23 21 20 18 17 15 14 12 11 10 8 6 5 3 2 0
LoU LoC
Reserved
Figure 3-16 Cache Level ID Register format
Table 3-37 shows how the bit values correspond with the Cache Level ID Register functions.
Table 3-38 shows the results of attempted access for each mode.
To access the Cache Level ID Register, read CP15 with:
CL 8 CL 7 CL 6 CL 5 CL 4 CL 3 CL 2 CL 1
Bits Field Function
MRC p15, 1, , c0, c0, 1 ; Read Cache Level ID Register
The purpose of the Silicon ID Register is to enable software to identify the silicon manufacturer
and revision. The reset value of this register is the SILICONID[31:0] input.
The Silicon ID Register is:
• a read-only register common for Secure and Nonsecure states
Table 3-37 Cache Level ID Register bit functions
[31:30] - Reserved, RAZ
[29:27] LoU 3'b001 = level of unification
[26:24] LoC 3'b010 = level of coherency
[23:21] CL 8 3'b000 = no cache at Cache Level (CL) 8
[20:18] CL 7 3'b000 = no cache at CL 7
[17:15] CL 6 3'b000 = no cache at CL 6
[14:12] CL 5 3'b000 = no cache at CL 5
[11:9] CL 4 3'b000 = no cache at CL 4
[8:6] CL 3 3'b000 = no cache at CL 3
[5:3] CL 2 3'b000 = no cache at CL 2
3'b100 = unified cache at CL 2
[2:0] CL 1 3'b011 = separate instruction and data cache at CL 1
Table 3-38 Results of access to the Cache Level ID Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Data Undefined Data Undefined Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
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