Cortex-A8 Technical Reference Manual - ARM Information Center

Value Description
System Control Coprocessor
0x06 Data read architecturally executed. This counter increments for every instruction that explicitly read data,
including SWP. This counter only increments for instructions that are unconditional or that pass their
condition codes.
0x07 Data write architecturally executed. The counter increments for every instruction that explicitly wrote data,
including SWP. This counter only increments for instructions that are unconditional or that pass their
condition codes.
0x08 Instruction architecturally executed. This counter counts for all instructions, including conditional
instructions that fail their condition codes.
0x09 Exception taken. This counts for each exception taken.
0x0A Exception return architecturally executed. This includes:
• RFE {!}
• MOVS PC (and other similar data processing instructions)
• LDM Rn{!},
This counter only increments for instructions that are unconditional or that pass their condition codes.
0x0B Instruction that writes to the Context ID Register architecturally executed. This counter only increments for
instructions that are unconditional or that pass their condition codes.
0x0C Software change of PC, except by an exception, architecturally executed. This counter only increments for
instructions that are unconditional or that pass their condition codes.
0x0D Immediate branch architecturally executed, taken or not taken. This includes B{L}, BLX, CB{N}Z, HB{L},
and HBLP. This counter counts for all immediate branch instructions that are architecturally executed,
including conditional instructions that fail their condition codes.
0x0E Procedure return, other than exception returns, architecturally executed. This includes:
• BX R14
• MOV PC, LR
• POP {..., PC}
• LDR PC, [R13], #offset
• LDMIA R9!, {...,PC}
• LDR PC, [R9], #offset
This counter only increments for instructions that are unconditional or that pass their condition codes.
0x0F Unaligned access architecturally executed. This counts each instruction that is an access to an unaligned
address. This counter only increments for instructions that are unconditional or that pass their condition
codes.
0x10 Branch mispredicted or not predicted. This counts for every pipeline flush because of a misprediction from
the program flow prediction resources.
0x11 Cycle count. This counts for every clock cycle.
0x12 Branches or other change in the program flow that could have been predicted by the branch prediction
resources of the processor.
0x13-0x3F Reserved.
0x40 Any write buffer full cycle.
0x41 Any store that is merged in the L2 memory system.
0x42 Any bufferable store transaction from load/store to L2 cache, excluding eviction or cast out data.
0x43 Any accesses to the L2 cache.
Table 3-97 Values for predefined events (continued)
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