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Cortex-A8 Technical Reference Manual - ARM Information Center

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System Control Coprocessor<br />

Table 3-144 shows how the bit values correspond with the Context ID Register functions.<br />

Bits Field Function<br />

3.2.73 c13, Thread and Process ID Registers<br />

Table 3-145 shows the results of attempted access for each mode.<br />

The current ASID value in the Context ID Register is exported to the MMU.<br />

To access the Context ID Register, read or write CP15 with:<br />

MRC p15, 0, , c13, c0, 1 ; Read Context ID Register<br />

MCR p15, 0, , c13, c0, 1 ; Write Context ID Register<br />

Table 3-144 Context ID Register bit functions<br />

[31:8] PROCID Extends the ASID to form the process ID and identifies the current process. The reset value is 0.<br />

[7:0] ASID Holds the ASID of the current process to identify the current ASID. The reset value is 0.<br />

Table 3-145 Results of access to the Context ID Register a<br />

Secure privileged Nonsecure privileged Secure User Nonsecure User<br />

Read Write Read Write Read Write Read Write<br />

Secure<br />

data<br />

Secure<br />

data<br />

Nonsecure<br />

data<br />

Nonsecure<br />

data<br />

Undefined Undefined Undefined Undefined<br />

a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the<br />

coprocessor instruction is executed.<br />

You must ensure that software executes a Data Synchronization Barrier operation before<br />

changes to this register. This ensures that all accesses are related to the correct context ID.<br />

You must execute an IMB instruction immediately after changes to the Context ID Register. You<br />

must not attempt to execute any instructions that are from an ASID-dependent memory region<br />

between the change to the register and the IMB instruction. Code that updates the ASID must<br />

execute from a global memory region.<br />

You must program each process with a unique number to ensure that the ETM and debug logic<br />

can correctly distinguish between processes.<br />

The purpose of the Thread and Process ID Registers is to provide locations to store the IDs of<br />

software threads and processes for OS management purposes.<br />

The Thread and Process ID Registers are:<br />

• three read/write registers banked for Secure and Nonsecure states:<br />

— user read/write Thread and Process ID Register<br />

— user read-only Thread and Process ID Register<br />

— privileged only Thread and Process ID Register.<br />

• accessible in different modes:<br />

— the user read/write Thread and Process ID Register is read/write in User and<br />

privileged modes<br />

— the user read-only Thread and Process ID Register is read-only in User mode, and<br />

read/write in privileged modes<br />

<strong>ARM</strong> DDI 0344K Copyright © 2006-2010 <strong>ARM</strong> Limited. All rights reserved. 3-123<br />

ID060510 Non-Confidential

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