Cortex-A8 Technical Reference Manual - ARM Information Center

Contents
2.14 The program status registers ................................................................................. 2-21
2.15 Exceptions ............................................................................................................. 2-27
2.16 Software consideration for Security Extensions .................................................... 2-34
2.17 Hardware consideration for Security Extensions ................................................... 2-35
2.18 Control coprocessor ............................................................................................... 2-38
Chapter 3 System Control Coprocessor
3.1 About the system control coprocessor ..................................................................... 3-2
3.2 System control coprocessor registers ...................................................................... 3-7
Chapter 4 Unaligned Data and Mixed-endian Data Support
4.1 About unaligned and mixed-endian data ................................................................. 4-2
4.2 Unaligned data access support ............................................................................... 4-3
4.3 Mixed-endian access support .................................................................................. 4-5
Chapter 5 Program Flow Prediction
5.1 About program flow prediction ................................................................................. 5-2
5.2 Predicted instructions .............................................................................................. 5-3
5.3 Nonpredicted instructions ........................................................................................ 5-6
5.4 Guidelines for optimal performance ......................................................................... 5-7
5.5 Enabling program flow prediction ............................................................................ 5-8
5.6 Operating system and predictor context .................................................................. 5-9
Chapter 6 Memory Management Unit
6.1 About the MMU ........................................................................................................ 6-2
6.2 Memory access sequence ....................................................................................... 6-3
6.3 16MB supersection support ..................................................................................... 6-4
6.4 MMU interaction with memory system ..................................................................... 6-5
6.5 External aborts ......................................................................................................... 6-6
6.6 TLB lockdown .......................................................................................................... 6-7
6.7 MMU software-accessible registers ......................................................................... 6-8
Chapter 7 Level 1 Memory System
7.1 About the L1 memory system .................................................................................. 7-2
7.2 Cache organization .................................................................................................. 7-3
7.3 Memory attributes .................................................................................................... 7-5
7.4 Cache debug ........................................................................................................... 7-7
7.5 Data cache features ................................................................................................. 7-8
7.6 Instruction cache features ........................................................................................ 7-9
7.7 Hardware support for virtual aliasing conditions .................................................... 7-10
7.8 Parity detection ...................................................................................................... 7-11
Chapter 8 Level 2 Memory System
8.1 About the L2 memory system .................................................................................. 8-2
8.2 Cache organization .................................................................................................. 8-3
8.3 Enabling and disabling the L2 cache controller ....................................................... 8-5
8.4 L2 PLE ..................................................................................................................... 8-6
8.5 Synchronization primitives ..................................................................................... 8-10
8.6 Locked access ....................................................................................................... 8-12
8.7 Parity and error correction code ............................................................................ 8-13
Chapter 9 External Memory Interface
9.1 About the external memory interface ....................................................................... 9-2
9.2 AXI control signals in the processor ........................................................................ 9-3
9.3 AXI instruction transactions ..................................................................................... 9-5
9.4 AXI data read/write transactions .............................................................................. 9-6
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