Cortex-A8 Technical Reference Manual - ARM Information Center

The PLE Identification and Status Register is:
• four read-only registers common to Secure and Nonsecure states
• accessible only in privileged modes.
System Control Coprocessor
Figure 3-53 shows the bit arrangement of the PLE Identification and Status Registers 0-3.
31 2 1 0
Reserved
Figure 3-53 PLE Identification and Status Registers format
Table 3-118 shows how the bit values correspond with the PLE Identification and Status
Registers functions.
Table 3-119 shows the Opcode_2 values for PLE channel function selection.
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CH1
CH0
Table 3-118 PLE Identification and Status Register bit functions
Bits Field Function
[31:2] - Reserved. UNP, SBZ.
[1] CH1 Provides information on PLE Channel 1 functions:
0 = PLE Channel 1 function disabled
1 = PLE Channel 1 function enabled. This is the reset value.
[0] CH0 Provides information on PLE Channel 0 functions:
0 = PLE Channel 0 function disabled
1 = PLE Channel 0 function enabled. This is the reset value.
Table 3-119 Opcode_2 values for PLE Identification and Status Register functions
Opcode_2 Function
0 Indicates channel present:
0 = channel is not present
1 = channel is present.
1 Reserved. Does not result in an Undefined Instruction
exception.
2 Indicates channel running:
0 = channel is not running
1 = channel is running.
3 Indicates channel interrupting:
0 = channel is not interrupting
1 = channel is interrupting, through completion or an error.
4-7 Reserved. Results in an Undefined Instruction exception.