Cortex-A8 Technical Reference Manual - ARM Information Center

processor
input ports
WEXTEST
WINTEST
WSE
Single WSE logic
11.2.2 Enabling sections of the core
processor
input ports
CAPTUREWR
TESTMODE
SERIALTEST
SHIFTWR
Hold control logic
Design for Test
Figure 11-27 Output wrapper boundary register cell control logic
The hold control logic in Figure 11-26 on page 11-28 and Figure 11-27 has capture and shift
signals that enable the WBR cell to hold data during test mode while both these signals are
deasserted. The only difference between the input wrapper and output wrapper cells is that the
WINTEST and WEXTEST connections switch polarity. The type of IEEE 1500
compliant-wrapper cell used with this logic is shown in Figure 11-28.
This utilization provides the benefit of requiring only one external wrapper scan enable and
preventing unknown states from being output from the WBR cells during patterns with multiple
capture cycles. If you use a standard multiplexed-scan flip-flop in the WBR in place of the WBR
cell as shown in Figure 11-28, you can use the shift_outputs and shift_inputs signals for the
scan enable to the output and input WBR cells, respectively.
Figure 11-28 shows the type of WBR cell required to meet IEEE 1500 compliance.
Functional input
capture_outputs_n
shift_outputs
Figure 11-28 IEEE 1500-compliant input wrapper boundary register cell
Note
The IEEE 1500-compliant output wrapper boundary register cell uses the shift_outputs and
capture_outputs_n signals.
Three Cortex-A8 signals control whether or not sections of the processor can update when
MBISTMODE is asserted or when TESTMODE is asserted. These signals are:
• TESTEGATE
• TESTNGATE
• TESTCGATE.
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SEin
Shift input
0
1
1
0
0
1
Hold
shift_inputs
D
SI
To output
WBR cells
Shift output
Q
capture_inputs_n
Functional output