Cortex-A8 Technical Reference Manual - ARM Information Center

EN b
3.2.43 c9, Count Enable Set Register
System Control Coprocessor
The PMNC Register is always accessible in privileged modes. Table 3-83 shows the results of
attempted access for each mode.
Table 3-83 Results of access to the Performance Monitor Control Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
0 Data Data Data Data Undefined Undefined Undefined Undefined
1 Data Data Data Data Data Data Data Data
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
b. The EN bit in c9, User Enable Register on page 3-89 enables User mode access of the Performance Monitor Registers.
To access the PMNC Register, read or write CP15 with:
MRC p15, 0, , c9, c12, 0 ; Read PMNC Register
MCR p15, 0, , c9, c12, 0 ; Write PMNC Register
The purpose of the CouNT ENable Set (CNTENS) Register is to enable or disable any of the
Performance Monitor Count Registers.
When reading this register, any enable that reads as 0 indicates the counter is disabled. Any
enable that reads as 1 indicates the counter is enabled.
When writing this register, any enable written with a value of 0 is ignored, that is, not updated.
Any enable written with a value of 1 indicates the counter is enabled.
The CNTENS Register is:
• a read/write register common to Secure and Nonsecure states
• accessible as determined by c9, User Enable Register on page 3-89.
Figure 3-39 shows the bit arrangement of the CNTENS Register.
31 30
4 3 2 1 0
C
Reserved
Figure 3-39 Count Enable Set Register format
Table 3-84 shows how the bit values correspond with the CNTENS Register functions.
ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 3-78
ID060510 Non-Confidential
P3
P2
P1
P0
Table 3-84 Count Enable Set Register bit functions
Bits Field Function
[31] C Enable cycle counter.
[30:4] - Reserved. UNP, SBZ.
[3] P3 Enable Counter 3.