Cortex-A8 Technical Reference Manual - ARM Information Center

3.1.3 MMU control and configuration
Security Extensions write access disable
System Control Coprocessor
The processor supports a primary input pin, CP15SDISABLE, to disable write access to the
CP15 registers.
When the CP15SDISABLE input is set to 1, any attempt to write to the secure version of the
banked register, NS-bit is 0, or any non-banked register, NS-state is 0 results in an Undefined
Instruction exception.
Changes in the pin on an instruction boundary occur as quickly as practically possible after a
change to this pin. Software must perform a IMB after a change to this pin has occurred on the
boundary of the macros to ensure that its effects are recognized on following instructions.
At reset, it is expected that this pin is set to logic 0 by the SoC hardware. Control of this pin is
expected to remain within the SoC chip that implements the processor.
Table 3-2 shows the CP15 registers affected by the primary input pin, CP15SDISABLE.
The purpose of the MMU control and configuration registers is to:
• allocate physical address locations from the Virtual Addresses (VAs) that the processor
generates
• control program access to memory
• configure translation table memory type attributes
• detect MMU faults and external aborts
• translate and lock translation table walk entries
• hold thread and process IDs.
Table 3-2 CP15 registers affected by CP15SDISABLE
Register Instruction
Control Register MCR p15, 0, , c1, c0, 0
Translation Table Base 0 MCR p15, 0, , c2, c0, 0
Translation Table Control Register MCR p15, 0, , c2, c0, 2
Domain Access Control MCR p15, 0, , c3, c0, 0
Primary Region Remap MCR p15, 0, , c10, c2, 0
Normal Memory Region Remap MCR p15, 0, , c10, c2, 1
Vector Base MCR p15, 0, , c12, c0, 0
Monitor Base MCR p15, 0, , c12, c0, 1
FCSE MCR p15, 0, , c13, c0, 0
Array operations MCR p15, 0, , c15, c0-15, 0-7
MRC p15, 0, , c15, c0-15, 0-7
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