Cortex-A8 Technical Reference Manual - ARM Information Center

Clock, Reset, and Power Control
3. Deassert DBGPWRDWNREQ to indicate that processor debug and ETM resources are
available. There is no requirement for hardware to wait for DBGPWRDWNACK to be
deasserted.
Note
The ETMPWRDWNREQ and ETMPWRDWNACK signals are not required because
debug and the ETM use the same power domain. ETMPWRDWNREQ must be tied to 0.
4. Continue a normal power-on reset sequence.
10.3.4 L1 data and L2 cache power domains
Powering up the integer core power domain while keeping NEON powered down
Apply the following sequence to power up the integer core while keeping NEON powered
down:
1. Apply power to the integer core power domain while keeping ARESETn,
ARESETNEONn and nPORESET asserted. Be sure to keep the NEON power domain
off.
2. Release the clamps to the debug PCLK, ETM CLK, and ETM ATCLK power domains
from the core by deasserting CLAMPCOREOUT and keeping CLAMPNEONOUT
asserted.
3. Deassert DBGPWRDWNREQ to indicate that processor debug and ETM resources are
available. There is no requirement for hardware to wait for DBGPWRDWNACK to be
deasserted.
Note
The ETMPWRDWNREQ and ETMPWRDWNACK signals are not required because
debug and the ETM use the same power domain. ETMPWRDWNREQ must be tied to 0.
4. Continue a normal power-on reset sequence while ARESETNEONn and
CLAMPNEONOUT remain asserted. To power up the NEON power domain, see
Powering up the NEON power domain while the processor is not in reset on page 10-17.
During periods when the entire core is not required, you can stop the processor clocks by
executing a Wait For Interrupt instruction. However, leakage continues to occur. To remove the
leakage component, you must remove the power supplied to the power domains within the
processor. However, the time required to remove and restore the power limits the advantage of
a full power-down of the processor. A full power-down sequence for the processor might
include:
1. Clean and invalidate the caches, L1 data and L2 caches, to the point of coherency.
2. Disable the L1 data and L2 cache.
3. Save off any TLB state such as locked entries, if required.
4. Save off architectural state.
5. Reset and power down the processor. See Powering down the integer core power domain
on page 10-18.
6. Power up the processor. See Powering up the integer core and NEON power domains on
page 10-18.
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