Cortex-A8 Technical Reference Manual - ARM Information Center

MCR p15, 0, , c8, c6, 0 ; Invalidate Data-TLB
MCR p15, 0, , c8, c6, 1 ; Invalidate Data-TLB entry (MVA)
MCR p15, 0, , c8, c6, 2 ; Invalidate Data-TLB (ASID)
MCR p15, 0, , c8, c7, 0 ; Invalidate Inst-TLB and Data-TLB
MCR p15, 0, , c8, c7, 1 ; Invalidate Inst-TLB and Data-TLB entry (MVA)
MCR p15, 0, , c8, c7, 2 ; Invalidate Inst-TLB and Data-TLB (ASID)
All other ARMv7-A TLB maintenance encodings are Unpredictable.
System Control Coprocessor
Functions that update the contents of the TLB occur in program order. Therefore, an explicit
data access before the TLB function uses the old TLB contents, and an explicit data access after
the TLB function uses the new TLB contents. For instruction accesses, TLB updates are
guaranteed to have taken effect before the next pipeline flush. This includes flush prefetch
buffer operations and exception return sequences.
Invalidate TLB unlocked entries
Invalidate TLB unlocked entries invalidates all the unlocked entries in the TLB.
Invalidate TLB Entry by MVA
For an area of memory to be remapped, you can use the Invalidate TLB Entry by MVA to
invalidate any TLB entry, locked or unlocked, by either:
• matching the MVA and ASID
• matching the MVA for a globally marked TLB entry.
The operation uses both the MVA and ASID as arguments. Figure 3-36 shows the format.
Invalidate TLB Entry on ASID Match
Figure 3-36 TLB Operations MVA and ASID format
This operation invalidates all TLB entries that match the provided ASID value. This function
invalidates locked entries but does not invalidate entries marked as global.
The Invalidate TLB Entry on ASID Match function requires an ASID as an argument.
Figure 3-37 shows the format.
3.2.42 c9, Performance Monitor Control Register
31 12 11 8 7
0
Modified virtual address
Reserved ASID
31 8 7
0
Reserved
Figure 3-37 TLB Operations ASID format
The purpose of the Performance MoNitor Control (PMNC) Register is to control the operation
of the four Performance Monitor Count Registers, and the Cycle Counter Register:
The PMNC Register is:
• a read/write register common to Secure and Nonsecure states
• accessible as determined by c9, User Enable Register on page 3-89.
ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 3-76
ID060510 Non-Confidential
ASID