Cortex-A8 Technical Reference Manual - ARM Information Center

System Control Coprocessor
Table 3-121 shows how the bit values correspond with the PLE User Accessibility Register
functions.
Bits Field Function
[31:2] - Reserved. UNP, SBZP.
Table 3-121 PLE User Accessibility Register bit functions
[1] U1 Indicates if a User mode process can access the registers for channel 1:
0 = User mode cannot access channel 1, reset value. User mode accesses cause an Undefined
Instruction exception.
1 = User mode can access channel 1.
[0] U0 Indicates if a User mode process can access the registers for channel 0:
0 = User mode cannot access channel 0, reset value. User mode accesses cause an Undefined
Instruction exception.
1 = User mode can access channel 0.
PLE
bit
Access in the Nonsecure state depends on the PLE bit, see c1, Nonsecure Access Control
Register on page 3-56. The processor can only access this register in privileged modes.
Table 3-122 shows the results of attempted access for each mode.
Table 3-122 Results of access to the PLE User Accessibility Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
0 Data Data Undefined Undefined Undefined Undefined Undefined Undefined
1 Data Data Data Data Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the
coprocessor instruction is executed.
To access the PLE User Accessibility Register, read or write CP15 with:
MRC p15, 0, , c11, c1, 0 ; Read PLE User Accessibility Register
MCR p15, 0, , c11, c1, 0 ; Write PLE User Accessibility Register
The registers that you can access in User mode when the U1 or U0 bit = 1 for the current channel
are:
• c11, PLE enable commands on page 3-109
• c11, PLE Control Register on page 3-109
• c11, PLE Internal Start Address Register on page 3-112
• c11, PLE Internal End Address Register on page 3-113
• c11, PLE Channel Status Register on page 3-114.
You can access the PLE Channel Number Register, see c11, PLE Channel Number Register on
page 3-108, in User mode when the U1 or U0 bit for any channel is 1.
The contents of these registers must be preserved on a task switch if the registers are user
accessible.
If the U bit for the currently selected channel is set to 0, and a User mode process attempts to
access any of these registers, the processor takes an Undefined instruction trap.
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