Cortex-A8 Technical Reference Manual - ARM Information Center

Note
The CTIINEN registers do not affect the CTIAPPPULSE operation.
15.6.6 CTI Trigger to Channel Enable Registers, CTIINEN0-8
Cross Trigger Interface
These registers are read/write registers that enable the signalling of an event on a CTM channel
or CTM channels when the core issues a CTITRIGIN trigger input to the CTI. There is one
register for each of the nine trigger inputs. Only seven trigger inputs are used, so CTIINEN7 and
CTIINEN8 are present but not used. Within each register there is one bit for each of the four
channels implemented. These registers do not affect the application trigger operations.
Figure 15-9 shows the bit arrangement of these registers.
Figure 15-9 CTI Trigger to Channel Enable Registers format
Table 15-9 shows how the bit values correspond with these registers.
Bits Field Function
31 4 3 0
[31:4] - Reserved. RAZ, SBZ.
15.6.7 CTI Channel to Trigger Enable Registers, CTIOUTEN0-8
These registers are read/write registers that define which channel can generate a
CTITRIGOUT output. There is one register for each of the nine CTITRIGOUT outputs.
Within each register there is one bit for each of the four channels implemented. These registers
affect the mapping from application trigger to trigger outputs.
Figure 15-10 shows the bit assignments of these registers.
Reserved TRIGINEN
Table 15-9 CTI Trigger to Channel Enable Registers bit functions
[3:0] TRIGINEN Enables a cross trigger event to the corresponding channel when CTITRIGIN is activated:
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the
CTM
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example, TRIGINEN[0] set to
1 in Register CTIINEN0, enables CTITRIGIN onto channel 0.
31 4 3
0
Reserved
TRIGOUTEN
Figure 15-10 CTI Channel to Trigger Enable Registers format
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