Cortex-A8 Technical Reference Manual - ARM Information Center

Clock, Reset, and Power Control
The voltage domains represent the power supply distributions that might be required in the
Cortex-A8 processor. These include:
Debug PCLK and ETM ATCLK
Connects to SoC debug power domain.
ETM CLK Operates at the same voltage as the processor but exists in same power domain as
debug.
NEON Operates at the same voltage as the processor and can be powered down while the
processor is running.
L2 RAMs Supports retention in the L2 cache, and supports SRAM voltage.
L1 data cache RAMs
Supports retention in the L1 data cache, and supports SRAM voltage.
Other L1 RAMs
Supports SRAM voltage.
Integer core
All logic within the integer core, not including SRAMs.
Any or all of these voltage domains can be removed from the processor. However, the removal
of those domains must comply with the supported power domain configurations listed in
Table 10-2 on page 10-13.
NEON power domain
If NEON is not required, you can reduce leakage by turning off the power to the NEON unit.
While the NEON unit is powered down, any Advanced SIMD instructions executed take the
Undefined Instruction exception. The OS uses the Undefined Instruction exception on an
Advanced SIMD instruction as a signal to apply power to the NEON unit, if powered down, or
to activate NEON, if disabled.
To enable NEON to be powered down, the implementation must place NEON on a separately
controlled power supply. In addition, the outputs of NEON must be clamped to benign values
while NEON is powered down, to indicate that NEON is idle.
Powering down the NEON power domain while the processor is in reset
To power down the NEON power domain while the processor is in reset, apply the following
sequence:
1. Assert both ARESETn and ARESETNEONn to place the processor in reset. You must
assert ARESETn and ARESETNEONn for at least eight CLK cycles before activating
the NEON clamps.
2. Activate the NEON output clamps by asserting the CLAMPNEONOUT input HIGH.
3. Remove power from the NEON power domain.
4. Deassert ARESETn, but continue to assert ARESETNEONn.
If the processor is executing a power-on reset sequence or is first powering up:
1. Assert both ARESETn and ARESETNEONn. You must assert ARESETn and
ARESETNEONn for at least eight CLK cycles before activating the NEON clamps.
2. Activate the NEON output clamps by asserting the CLAMPNEONOUT input HIGH.
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