Cortex-A8 Technical Reference Manual - ARM Information Center

System Control Coprocessor
Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH
result in an Undefined Instruction exception, see Security Extensions write access disable on
page 3-5.
Table 3-117 shows the results of attempted access for each mode.
To access the Memory Region Remap Registers read or write CP15 with:
MRC p15, 0, , c10, c2, 0 ; Read Primary Region Remap Register
MCR p15, 0, , c10, c2, 0 ; Write Primary Region Remap Register
MRC p15, 0, , c10, c2, 1 ; Read Normal Memory Remap Register
MCR p15, 0, , c10, c2, 1 ; Write Normal Memory Remap Register
Memory remap occurs in two stages:
1. The processor uses the Primary Region Remap Register to remap the primary memory
type, normal, device, or strongly ordered, and the shareable attribute.
2. For memory regions that the Primary Region Remap Register defines as Normal memory,
the processor uses the Normal Memory Remap Register to remap the inner and outer
cacheable attributes.
The behavior of the Memory Region Remap Registers depends on the TEX Remap bit, see c1,
Control Register on page 3-44. If the TEX Remap bit is set to 1, the entries in the Memory
Region Remap Registers remap each possible value of the TEX[0], C and B bits in the
translation tables. You can therefore set your own definitions for these values. If the TEX
Remap bit is cleared to 0, the Memory Region Remap Registers are not used and no memory
remapping takes place. See MMU software-accessible registers on page 6-8 for more
information.
The Memory Region Remap Registers are expected to remain static during normal operation.
When you write to the Memory Region Remap Registers, you must invalidate the TLB and
perform an IMB operation before you can rely on the new written values. You must also stop
the PLE if it is running.
Note
For security reasons, you cannot remap the NS bit.
3.2.59 c11, PLE Identification and Status Registers
Table 3-117 Results of access to the memory region remap registers a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Secure
data
Secure
data
Nonsecure
data
Nonsecure
data
Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the
coprocessor instruction is executed.
The purpose of the PLE Identification and Status Registers is to define:
• the PLE channels that are physically implemented on the particular device
• the current status of the PLE channels.
Processes that handle PLE can read this register to determine the physical resources
implemented and their availability.
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