Cortex-A8 Technical Reference Manual - ARM Information Center

U
bit
PLE
bit
Table 3-129 shows the results of attempted access for each mode.
System Control Coprocessor
To access the PLE Internal Start Address Register, set the PLE Channel Number Register to the
appropriate PLE channel and read or write CP15 c11 with:
MRC p15, 0, , c11, c5, 0 ; Read PLE Internal Start Address Register
MCR p15, 0, , c11, c5, 0 ; Write PLE Internal Start Address Register
3.2.65 c11, PLE Internal End Address Register
Table 3-129 Results of access to the PLE Internal Start Address Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
0 0 Data Data Undefined Undefined Undefined Undefined Undefined Undefined
1 Data Data Data Data Undefined Undefined Undefined Undefined
1 0 Data Data Undefined Undefined Data Data Undefined Undefined
1 Data Data Data Data Data Data Data Data
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
The purpose of the PLE Internal End Address Register for each channel is to define the number
of cache lines transferred.
The PLE Internal End Address Register is:
• a 32-bit read/write register with one register for each PLE channel common to Secure and
Nonsecure states
• accessible in User and privileged modes.
Figure 3-58 shows the bit arrangement of the PLE Internal End Address Register functions.
31 N N-1 6 5
0
Reserved
Reserved
Figure 3-58 PLE Internal End Address Register format
The PLE Internal End Address Register bits [N:6] contain the number of cache lines transferred
where N is determined by the L2 cache size as defined in Table 3-130.
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Lines
Table 3-130 Maximum transfer size for various L2 cache sizes
Cache size N Maximum number of lines Maximum transfer size
0KB 6 0 0KB a
128KB 14 256 16KB
256KB 15 512 32KB
512KB 16 1024 64KB
1024KB 17 2048 128KB