Cortex-A8 Technical Reference Manual - ARM Information Center

Bits Field Function
[11:8] L1 Harvard cache line
maintenance operations
by set and way
[7:4] L1 unified cache line
maintenance operations
by MVA
[3:0] L1 Harvard cache line
maintenance operations
by MVA
3.2.13 c0, Memory Model Feature Register 2
Table 3-22 shows the results of attempted access for each mode.
To access the Memory Model Feature Register 1, read CP15 with:
MRC p15, 0, , c0, c1, 5 ; Read Memory Model Feature Register 1
System Control Coprocessor
Table 3-21 Memory Model Feature Register 1 bit functions (continued)
Indicates support for L1 cache line maintenance operations by set and way,
Harvard architecture.
0x0 = Processor supports:
• clean data cache line by set and way
• clean and invalidate data cache line by set and way
• invalidate data cache line by set and way
• invalidate instruction cache line by set and way.
Indicates support for L1 cache line maintenance operations by MVA, unified
architecture:
0x0 = no support in processor.
Indicates support for L1 cache line maintenance operations by MVA, Harvard
architecture.
0x0 = Processor supports:
• clean data cache line by MVA
• invalidate data cache line by MVA
• invalidate instruction cache line by MVA
• clean and invalidate data cache line by MVA
• invalidation of branch target buffer by MVA.
Table 3-22 Results of access to Memory Model Feature Register 1 a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Data Undefined Data Undefined Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
The purpose of the Memory Model Feature Register 2 is to provide information about the
memory model, memory management, cache support, and TLB operations of the processor.
The Memory Model Feature Register 2 is:
• a read-only register common to the Secure and Nonsecure states
• accessible in privileged modes only.
Figure 3-9 on page 3-30 shows the bit arrangement of the Memory Model Feature Register 2.
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